The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement to reduce an ON voltage while sustaining a high breakdown voltage and ensuring a wide operating area.
FIG. 41 is a cross-sectional elevation of a conventional insulated gate bipolar transistor (hereinafter, referred to as xe2x80x9cIGBTxe2x80x9d) in the background art of the present invention. In this device 150, as is in general in a power semiconductor device, a lot of unit cells UC connected in parallel are incorporated in a single semiconductor base body 93 in order to gain a large main current. The unit cells UC are minimum units constituting the device 150 and each has an IGBT structure, serving as an IGBT. FIG. 41 shows one unit cell UC.
The device 150 has a structure of so-called xe2x80x9cvertical-typexe2x80x9d and xe2x80x9cplanar-typexe2x80x9d IGBT. The xe2x80x9cvertical-typexe2x80x9d one has a structure in which a pair of main electrodes are connected to one and the other of two main surfaces of a semiconductor base body 93 and the xe2x80x9cplanar-typexe2x80x9d one has a structure in which a gate electrode is opposed in parallel to one of the main surfaces of the semiconductor base body 93. In the device 150, the semiconductor base body 93 whose base material is a silicon comprises a p collector layer 81 and an n layer 82. The n layer 82 comprises an n+ buffer layer 95 having a junction between the p collector layer 81 and itself and an n+ layer 83 exposed to an upper main surface of the semiconductor base body 93. The p collector layer 81 is exposed to a lower main surface of the semiconductor base body 93.
A p base layer 84 is selectively formed in a surface to which the nxe2x88x92 layer 83 is exposed, and an n+ emitter layer 85 is selectively formed in a surface to which the p base layer 84 is exposed. The n+ emitter layer 85 is formed to be shallower than the p base layer 84 and inside the p base layer 84. Further, the n+ emitter layer 85 is divided into two regions in a single p base layer 84. Therefore, a first region of the p base layer 84 sandwiched by the two divided regions of the n+ emitter layer 85 and two second regions of the p base layer 84 sandwiched by the two divided regions and the nxe2x88x92 layer 83, respectively, are selectively exposed in the upper main surface of the semiconductor base body 93.
An emitter electrode 89 is connected to the first region to which the p base layer 84 is exposed and part of a surface to which the n+ emitter layer 85 is exposed in the upper main surface of the semiconductor base body 93. Further, a gate insulating film 87 and a gate electrode 88 are formed on the second region of the p base layer 84. Specifically, the gate electrode 88 is opposed to the second region of the p base layer 84 with the gate insulating film 87 sandwiched therebetween. As a result, the second region serves as a channel region CH. A collector electrode 94 is connected to the lower main surface of the semiconductor base body 93, i.e., the surface to which the p collector layer 81 is exposed. The emitter electrode 89 and the collector electrode 94 serve as a pair of main electrodes.
When the device 150 is used, a power supply is connected (usually through a load) between the emitter electrode 89 and the collector electrode 94. A collector voltage is thereby applied between the collector electrode 94 and the emitter electrode 89 so that a potential at the collector electrode 94 may become positive with the emitter electrode 89 as a reference. In this state, by controlling a voltage applied to the gate electrode 88, i.e., a gate voltage with the emitter electrode 89 as a reference, the magnitude of a main current (collector current) flowing from the collector electrode 94 to the emitter electrode 89 can be controlled.
When a positive gate voltage higher than a gate threshold voltage inherent to the device 150 is applied, the channel region CH positioned immediately below the gate electrode 88 is inverted from natural p type to n type. Specifically, an n-type inversion layer is formed in the channel region CH. As a result, electrons flowing from the emitter electrode 89 through the n+ emitter layer 85 is injected into the nxe2x88x92 layer 83 through the channel region CH.
Since a portion between the p collector layer 81 and the n layer 82 (including the nxe2x88x92 layer 83 and the n+ buffer layer 95) is biased in the forward direction by the implanted electrons, holes are injected from the p collector layer 81 into the nxe2x88x92 layer 83. That causes modulation of conductivity to largely reduce the resistance of the nxe2x88x92 layer 83, and therefore a large main current flows from the collector electrode 94 to the emitter electrode 89. In other words, the device 150 is brought into conduction (an ON state).
Next, when the gate voltage is returned to zero or negative value, the channel region CH is returned to the natural p type. As a result, since the injection of the electrons from the emitter electrode 89 is stopped, the injection of the hole from the p collector layer 81 is also stopped. After that, the holes accumulated in the nxe2x88x92 layer 83 (and the n+ buffer layer 95) are retrieved in the emitter electrode 89 and then extinguished. In other words, the device 150 is brought into a cut-off state (an OFF state).
Thus, the device 150 having the IGBT structure has an advantage that the collector voltage in the ON state, i.e., the ON voltage is low because the modulation of conductivity is used. In the IGBT, generally, the ON voltage VCE (SAT) is expressed by Eq. 1.
xe2x80x83VCE(sat)=VMOS+VDIODExe2x80x83xe2x80x83(Eq. 1)
where VMOS represents a voltage drop (ON voltage of a MOSFET) developed in a MOSFET equivalently constituted of the n+ emitter layer 85, the channel region CH and the nxe2x88x92 layer 83 and VDIODE represents a voltage drop (ON voltage of a diode) developed in a diode equivalently constituted of the p collector layer 81 and the n layer 82. As shown in Eq. 1, the ON voltage VCE(sat) can be divided into two components.
Further, when the IGBT is in the ON state, the resistance R of the nxe2x88x92 layer 83 which causes the modulation of conductivity is expressed by Eq. 2.
Rxe2x88x9dW2/(2xc2x7{square root over ( )}(Dxc2x7xcfx842))xe2x80x83xe2x80x83(Eq. 2)
where W represents the thickness of the nxe2x88x92 layer 83, D represents a diffusion coefficient of the hole and xcfx84 represents the lifetime of the hole in the nxe2x88x92 layer 83. As shown in Eq. 2, the resistance R of the nxe2x88x92 layer 83 depends on the thickness W of the nxe2x88x92 layer 83 and the lifetime xcfx84.
In order to achieve an IGBT of high breakdown voltage, it is necessary to set the thickness D of the nxe2x88x92 layer 83 larger. For this reason, in the IGBT of high breakdown voltage, the ratio of the voltage drop VDIODE developed in the diode among the two components constituting the ON voltage VCE(sat) is high. In other words, in the IGBT of high breakdown voltage, reducing the ON voltage of the diode is more effective in reducing the ON voltage VCE(sat) than reducing the ON voltage of the MOSFET.
In this direction, as a semiconductor device with reduced On voltage VCE(sat), Kitagawa et al. proposes Injection Enhanced Transistor (IEGT) (xe2x80x9cIEDMxe2x80x9d (1993) pp. 679 to 682) and Takahashi et al. proposes Carrier Stored Trench-Gate bipolar Transistor (CSTBT) (xe2x80x9cISPSDxe2x80x9d (1996) pp. 349 to 352). In the IEGT, part of a p base layer is not short circuited with an emitter electrode. That allows accumulation of a hole current injected from a p collector layer in an emitter region. As a result, since the carrier concentration near an emitter layer is increased and the modulation of conductivity is accelerated, the ON voltage VDIODE of a diode is improvingly lowered.
Further, in the CSTBT, an n+ layer of relatively high impurity concentration is formed immediately below a p base layer. That allows accumulation of a hole current implanted from a p collector layer in an emitter layer, like in the IEGT. As a result, since the carrier concentration near the emitter layer is increased and the modulation of conductivity is accelerated, the ON voltage VDIODE of a diode is improvingly lowered.
The above two types of devices are reported as semiconductor devices each having a gate electrode buried in a trench formed in an upper main surface of a semiconductor base body (i.e., trench gate), i.e., xe2x80x9ctrench-typexe2x80x9d devices. Also in the semiconductor device having the gate electrode 88 opposed to the upper main surface of the semiconductor base body 93, i.e., the xe2x80x9cplanar-typexe2x80x9d device, like the device 150 (FIG. 41), however, the same effect is expected. A xe2x80x9cplanar-typexe2x80x9d IEGT can be achieved by reducing the ratio of a region in which the MOSFET is formed (hereinafter, referred to as xe2x80x9cMOSFET regionxe2x80x9d) in the main surface of the semiconductor base body and restricting a path through which the hole current flows to the emitter electrode 89 to be narrow.
In order to confirm this, we calculate the three kinds of On voltages VCE(sat), VDIODE and VMOS by using simulation in a case where the ratio of the MOSFET region varies in the xe2x80x9cplanar-typexe2x80x9d IGBT shown in FIG. 41. Concurrently, in the simulation, the effect produced when the thickness of the nxe2x88x92 layer 83 varies is also checked. The obtained result is shown in the graph and table of FIGS. 42 and 43, respectively.
In order to change the ratio of the MOSFET region, the width Wcell of the unit cell UC (cell width) is varied while the width Wcd of an opening (opening width) of the gate electrode 88 is kept constant. In other words, a variety of ratios of the MOSFET region can be obtained by varying the cell width Wcell while keeping the width Wp of the p base layer 84 (base width) constant. In the first to third columns of FIG. 43, the numerical values of the cell width Wcell, the opening width Wcd, and the width Wg of the gate electrode (Wg=Wcellxe2x88x92Wcd) are shown in xcexcm.
Further, the MOSFET region ratio xcex1 shown in FIGS. 42 and 43 is defined by the p base region ratio expressed by Eq. 3.
xcex1=Wp/Wcellxe2x80x83xe2x80x83(Eq. 3)
Furthermore, the numeral values, e.g., xe2x80x9c(250 xcexcm)xe2x80x9d applied to the ON voltages VCD(sat) and VDIODE indicate the thickness of the nxe2x88x92 layer 83 (the depth of an interface between the nxe2x88x92 layer 83 and the n+ buffer layer 95 with the upper main surface of the semiconductor base body 93 as a reference). The numeral values of the On voltages VCE(sat), VDIODE and VMOS in FIG. 43 are shown in volt (V).
First, FIG. 42 makes it clear that the On voltage VMOS of the MOSFET becomes higher while the ON voltage VDIODE of the diode becomes lower as the MOSFET region ratio xcex1 decreases. Secondly, it is clearly shown that the ratio of the On voltage VDIODE of the diode in the ON voltage VCE(sat) of the IGBT becomes higher as the thickness of the nxe2x88x92 layer 83 increases. In other words, the result of the simulation supports that reducing the MOSFET region ratio a effectively contributes to reduction in the ON voltage VCE(sat) of the IGBT in the device of high breakdown voltage in which the nxe2x88x92 layer 83 is set thick.
In the xe2x80x9cplanar-typexe2x80x9d device, however, there are some problems in achieving both high breakdown voltage and low ON voltage. One of the problems is that since reducing the MOSFET region ratio xcex1 is equivalent to reduction in the ratio of the p base layer 84, the density of the hole current flowing in the p base layer 84 becomes higher when the device is turned off (shifted from the ON state to the OFF state). When the density of the hole current flowing in the p base layer 84 becomes higher at the turning-off, for example, an operating area evaluated by the SOA becomes narrower.
On the other hand, in order to achieve a xe2x80x9cplanar-typexe2x80x9d CSTBT, it is only necessary to form an n+ layer immediately below the p base layer 84 and not necessary to reduce the MOSFET region ratio xcex1, and therefore the problem of narrower operating area can be avoided. In such a structure, however, since the strength of an electric field caused by application of reverse voltage, there arises another problem of degradation of the breakdown voltage. Further, it is said that the cause of operation failure due to cosmic ray is closely related to the electric field strength, and there is possibility of an increase of failure incidence.
Thus, in the xe2x80x9cplanar-typexe2x80x9d semiconductor device in the background art, it is disadvantageously difficult to ensure reduction in the ON voltage while sustaining a high breakdown voltage and ensuring a wide operating area.
The present invention is intended to solve the above problems and an object of the present invention is to provide a semiconductor device which can reduce an ON voltage while sustaining a high breakdown voltage and ensuring a wide operating area. Further, another object of the present invention is to provide a method suitable for manufacturing such a semiconductor device.
According to a first aspect of a semiconductor device of the present invention, the semiconductor device comprises a semiconductor base body defining an upper main surface and a lower main surface, and the semiconductor base body comprises a first semiconductor layer of a first conductivity type exposed to the lower main surface; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and exposed to the upper main surface; a third semiconductor layer of the first conductivity type selectively formed in the upper main surface, being shallower than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively formed in a surface to which the third semiconductor layer is exposed, being shallower than the third semiconductor layer and inside the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in the upper main surface, being shallower than the second semiconductor layer and away from the third semiconductor layer; a sixth semiconductor layer of the second conductivity type selectively formed in a surface to which the fifth semiconductor layer is exposed, being shallower than the fifth semiconductor layer and inside the fifth semiconductor layer; and a seventh semiconductor layer of the first conductivity type selectively formed in a surface to which the sixth semiconductor layer is exposed, being shallower than the sixth semiconductor layer and inside the sixth semiconductor layer.
Moreover, a surface to which the third semiconductor layer is exposed in the upper surface includes a first region and a second region separated by the fourth semiconductor layer, and at least the second region of them is sandwiched by a surface to which the fourth semiconductor layer is exposed and a surface to which the second semiconductor layer is exposed, and the device further comprises: a first gate electrode opposed to the second region with a first insulating film sandwiched therebetween; a second gate electrode opposed to a surface to which the sixth semiconductor layer is exposed in said upper surface with a second insulating film sandwiched therebetween; a first main electrode connected to the first region, the fourth semiconductor layer and the seventh semiconductor layer; and a second main electrode connected to the lower main surface.
According to a second aspect of the semiconductor device of the present invention, in the first aspect, the first gate electrode and the second gate electrode are electrically connected to each other.
According to a third aspect of the semiconductor device of the present invention, in the second aspect, the first insulating film and the second insulating film are contiguously coupled to form a single insulating film, and the first gate electrode and the second gate electrode are contiguously coupled to form a single gate electrode, and a surface to which the second semiconductor layer is exposed with the same sandwiched between the third semiconductor layer and the seventh semiconductor layer in the upper main surface is covered with the single gate electrode with the single insulating film sandwiched therebetween.
According to a fourth aspect of the semiconductor device of the present invention, in the second aspect, an area of the first gate electrode covering the upper main surface is larger that of the second gate electrode covering the upper main surface, and the first gate electrode and the second gate electrode are connected to each other at an end portion along the upper main surface.
According to a fifth aspect of the semiconductor device of the present invention, in the first aspect, the first gate electrode and the second gate electrode are electrically insulated from each other.
According to a sixth aspect of the semiconductor device of the present invention, in the first aspect, the semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type formed in the surface to which the sixth semiconductor layer is exposed in the upper main surface.
According to a seventh aspect of the semiconductor device of the present invention, in the first aspect, the semiconductor base body further comprises an eighth semiconductor layer of the first conductivity type selectively formed in an exposed surface which is a surface to which the second semiconductor layer is exposed in the upper main surface, being shallower than the second semiconductor layer and away from both the third and fifth semiconductor layers.
According to an eighth aspect of the semiconductor device of the present invention, in the seventh aspect, the first insulating film and the first gate electrode are so extended as to also cover a portion adjacent to the third semiconductor layer in the exposed surface, and the second insulating film and the second gate electrode are so extended as to also cover a portion adjacent to the fifth semiconductor layer in the exposed surface, and a surface portion covered with neither the first gate electrode nor the second gate electrode exists in the exposed surface, and the eighth semiconductor layer is selectively formed in a region including the surface portion in the exposed surface.
According to a ninth aspect of the semiconductor device of the present invention, in the eighth aspect, the third semiconductor layer, the fifth semiconductor layer and the eighth semiconductor layer are identical in depth and impurity concentration with one another.
According to a tenth aspect of the semiconductor device of the present invention, in the first aspect, a multilayer structure including the fifth, sixth and seventh semiconductor layers is divided into a plurality of unit multilayer structures formed away from one another, the second insulating film and the second gate electrode comprise a plurality of unit second insulating films and a plurality of unit second gate electrodes, respectively, any one of the plurality of unit second gate electrodes is opposed to a surface to which a portion of the sixth semiconductor layer included in corresponding one of the plurality of unit multilayer structures is exposed in the upper main surface with corresponding one of the plurality of unit second insulating films sandwiched therebetween, and the first main electrode is connected to a portion of the seventh semiconductor layer included in each of the plurality of unit multilayer structures.
According to an eleventh aspect of the semiconductor device of the present invention, in the first aspect, a multilayer structure including the fifth, sixth and seventh semiconductor layers is so annularly formed as to surround the third semiconductor layer.
According to a twelfth aspect of the semiconductor device of the present invention, in the first aspect, the semiconductor base body further comprises an eighth semiconductor layer of the second conductivity type having an impurity concentration higher than that of the third semiconductor layer, selectively formed in a region inside edges of the third semiconductor layer in the upper main surface, being exposed to the first region and not exposed to the second region, and the first main electrode is connected to the third semiconductor layer through the eighth semiconductor layer.
According to a thirteenth aspect of the semiconductor device of the present invention, in the twelfth aspect, the seventh semiconductor layer and the eighth semiconductor layer are identical in depth and impurity concentration with each other.
According to a fourteenth aspect of the semiconductor device of the present invention, in the first aspect, the third semiconductor layer and the fifth semiconductor layer are identical in depth and impurity concentration with each other.
According to a first aspect of a manufacturing method of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor base body defining an upper main surface and a lower main surface and comprising a first semiconductor layer of a first conductivity type exposed to the lower main surface and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and exposed to the upper main surface; (b) selectively introducing an impurity of the first conductivity type into the upper main surface to selectively form a third semiconductor layer of the first conductivity type to be shallower than the second semiconductor layer in the upper main surface; (c) selectively introducing the impurity of the first conductivity type into the upper main surface to selectively form a fifth semiconductor layer of the first conductivity type to be shallower than the second semiconductor layer and away from the third semiconductor layer in the upper main surface; and (d) selectively introducing an impurity of the second conductivity type into the upper main surface to selectively form a fourth semiconductor layer of the second conductivity type to be shallower than the third semiconductor layer and inside the third semiconductor layer in a surface to which the third semiconductor layer is exposed.
Moreover, the fourth semiconductor layer is formed in the step (d) so that a surface to which the third semiconductor layer is exposed in the upper surface includes a first region and a second region separated by the fourth semiconductor layer and at least the second region of them is sandwiched by a surface to which the fourth semiconductor layer is exposed and a surface to which the second semiconductor layer is exposed, and the manufacturing method further comprises the steps of: (e) selectively introducing the impurity of the second conductivity type into the upper main surface to selectively form a sixth semiconductor layer of the second conductivity type to be shallower than the fifth semiconductor layer and inside the fifth semiconductor layer in a surface to which the fifth semiconductor layer is exposed, (f) selectively introducing the impurity of the first conductivity type into the upper main surface to selectively form a seventh semiconductor layer of the first conductivity type to be shallower than the sixth semiconductor layer and inside the sixth semiconductor layer in a surface to which the sixth semiconductor layer is exposed; (g) selectively forming a first insulating film and a second insulating film in the upper main surface; (h) forming a first gate electrode and a second gate electrode on the first insulating film and the second insulating film, respectively; (i) connecting a first main electrode to the first region, the fourth semiconductor layer and the seventh semiconductor layer; and (j) connecting a second main electrode to the lower main surface.
Moreover, the steps (b) to (h) are performed so that the first gate electrode is opposed to the second region and the second gate electrode is opposed to a surface in which the sixth semiconductor layer is exposed in the upper main surface.
According to a second aspect of the manufacturing method of the present invention, in the first aspect, the steps (g) and (h) are performed before the steps (b) and (c), and the impurity of the first conductivity type is selectively implanted in the upper main surface with the first gate electrode and the second gate electrode used as shields and thereafter diffused to form the third semiconductor layer and the fifth semiconductor layer at the same time in the steps (b) and (c).
According to a third aspect of the manufacturing method of the present invention, in the second aspect, the first insulating film and the second insulating film are so formed as to be contiguously coupled to form a single insulating film in the step (g), and the first gate electrode and the second gate electrode are so formed as to be contiguously coupled to form a single gate electrode in the step (h).
According to a fourth aspect of the manufacturing method of the present invention, in the second aspect, the impurity of the first conductivity type is selectively implanted in the upper main surface with the first gate electrode and the second gate electrode used as shields and thereafter diffused to form the third semiconductor layer and the fifth semiconductor layer and selectively form an eighth semiconductor layer of the first conductivity type at the same time in the upper surface to be shallower than the second semiconductor layer and away from both the third semiconductor layer and the fifth semiconductor layer in the steps (b) and (c).
According to a fifth aspect of the manufacturing method of the present invention, in the first aspect, the step (f) comprises the steps of (f-1) selectively forming a shield over the upper main surface; and (f-2) selectively implanting the impurity of the first conductivity type in the upper main surface by using the shield and thereafter diffusing it to form the seventh semiconductor layer and form an eighth semiconductor layer of the first conductivity type having an impurity concentration higher than that of the third semiconductor layer in a region inside edges of the third semiconductor layer in the upper main surface to be exposed to the first region and not to be exposed to the second region.
In the semiconductor device of the first aspect of the present invention, a first channel region is formed in the second region of the third semiconductor layer opposed to the first gate electrode and a second channel region having the conductivity type opposite to that of the first channel region is formed in the exposed surface of the sixth semiconductor layer opposed to the second gate electrode. When a predetermined gate voltage is applied to the first and second gate electrodes so that an inversion layer may be formed in the first channel, the device is brought into conduction. At this time, a main current mainly constituted of the carriers generated in the first semiconductor layer, i.e., minority carriers in the second semiconductor layer does not flow in the fifth semiconductor layer but exclusively flows in the third semiconductor layer. Therefore, by the carrier accumulation effect, the ON voltage can be suppressed low.
On the other hand, when to cut off the device, the predetermined gate voltage is applied to the first and second gate electrodes so that the inversion layer may be formed in the second channel, a main current constituted of residual carriers flows both in the third and fifth semiconductor layers. Since that reduces the density of the main current flowing in the third semiconductor layer during the turn-off, a withstand turn-off voltage is enhanced and a wide operating area is ensured. Further, since unlike in the CSTBT, no semiconductor layer of the second conductivity type surrounding the third semiconductor layer is needed, there arises no problem of degradation in breakdown voltage caused by that semiconductor layer. In other words, it is possible to achieve reduction in ON voltage while sustaining a high breakdown voltage and ensuring a wide operating area.
In the semiconductor device of the second aspect of the present invention, since the first and second gate electrodes are electrically connected to each other, it is not necessary to individually apply the gate voltage thereto.
In the semiconductor device of the third aspect of the present invention, since the exposed surface of the second semiconductor layer sandwiched between the third semiconductor layer and the seventh semiconductor layer is covered with the gate electrode, an even potential gradient is obtained and the electric field concentration can be relieved. Therefore, the breakdown voltage of the device is enhanced.
In the semiconductor device of the fourth aspect of the present invention, since the area of the first gate electrode covering the upper main surface is larger than that of the second gate electrode covering the upper main surface, a parasitic capacitance between the first gate electrode and the semiconductor substrate is larger. For this reason, even when the same gate voltage is applied to the end portions thereof, a change in voltage in the second gate electrode is faster than that in the first gate electrode. As a result, only by externally applying a single gate electrode, the concentration of the main current in the third semiconductor layer during the turn-off can further be relieved.
In the semiconductor device of the fifth aspect of the present invention, since the two gate electrodes are electrically insulated, it is possible to individually input the gate voltage so that the voltage at the second gate electrode is changed faster than that at the first gate electrode when the device is turned off. It thereby becomes possible to further relieve the concentration of the main current in the third semiconductor layer during the turn-off.
In the semiconductor device of the sixth aspect of the present invention, since the eighth semiconductor layer of the same conductivity type as the third semiconductor layer is formed in the surface to which the sixth semiconductor layer is exposed, the conductivity types of the first channel region and the second channel region become common. For this reason, in order to bring the device into conduction, by commonly applying the predetermined gate voltage to the first and second gate electrodes so that the inversion layers can be formed both in the channel regions, it becomes possible to restrict the path of the main current to the third semiconductor layer. That enhances the carrier accumulation effect and suppresses the ON voltage low.
On the other hand, in order to bring the device in the cut-off state, it is only necessary to commonly apply zero voltage to the first and second gate electrodes so that the inversion layer may disappear both in the channel regions. At this time, since the sixth semiconductor layer is electrically connected to the first main electrode through the eighth semiconductor layer, the main current constituted of the residual carriers flows both in the third and fifth semiconductor layers. Therefore, the withstand turn-off voltage can be enhanced and the operating area can be widely ensured. In other words, high convenience in use is achieved since it is not necessary to apply any negative voltage as a gate voltage in order to ensure reduction in the ON voltage without narrowing the operating area.
In the semiconductor device of the seventh aspect of the present invention, since the eighth semiconductor layer is selectively formed in the surface to which the second semiconductor layer is exposed, a boundary of depletion layers is made even. That enhances the breakdown voltage of the device.
In the semiconductor device of the eighth aspect of the present invention, since the eighth semiconductor layer is formed in a portion covered with neither the first gate electrode nor the second gate electrode in the exposed surface of the second semiconductor layer, the electric field concentration in the portion covered with neither the first gate electrode nor the second gate electrode is relieved and the degradation in breakdown voltage can be suppressed.
In the semiconductor device of the ninth aspect of the present invention, since the third, fifth and ninth semiconductor layers are identical in depth and impurity concentration, these semiconductor layers can be formed at the same time in a single process using the same shield. In other words, it is possible to facilitate the manufacturing process.
In the semiconductor device of the tenth aspect of the present invention, since there are a plurality of multilayer structures, more second channel regions each serving as a path in which the main current flows during the turn-off are provided as compared with a case where there is one multilayer structure. Therefore, the concentration of the main current in the third semiconductor layer can be further relieved.
In the semiconductor device of the eleventh aspect of the present invention, since the multilayer structure is so annularly formed as to surround the third semiconductor layer, the channel width of the second channel region is larger than that of the first channel region. Moreover, it is possible to easily set the MOSFET region ratio low. Therefore, the ON voltage can be further reduced while the wide operating area is kept.
In the semiconductor device of the twelfth aspect of the present invention, the eighth semiconductor layer having an impurity concentration higher than that of the third semiconductor layer is provided and connected to the first main electrode. Therefore, since the potential difference between the third semiconductor layer and the fourth semiconductor layer developed by passage of the main current can be suppressed low, the withstand latch-up voltage can be enhanced.
In the semiconductor device of the thirteenth aspect of the present invention, since the seventh semiconductor layer and the eighth semiconductor layer are common in depth and impurity concentration, these semiconductor layers can be formed at the same time in a single process using the same shield. In other words, it is possible to facilitate the manufacturing process.
In the semiconductor device of the fourteenth aspect of the present invention, since the third semiconductor layer and the fifth semiconductor layer are common in depth and impurity concentration, these semiconductor layers can be formed at the same time in a single process using the same shield. In other words, it is possible to facilitate the manufacturing process.
In the method of manufacturing a semiconductor device of the first aspect of the present invention, the semiconductor device of the first aspect can be easily manufactured by combining ordinary wafer processes including a process step of introducing the impurity.
In the method of manufacturing a semiconductor device of the second aspect of the present invention, the first and second gate electrodes are formed at the same time, and the third and fifth semiconductor layers are formed at the same time by implanting the impurity with these electrodes used as shields. That brings, as an effect, an efficient manufacture with less number of process steps, and makes it possible to determine the positional relation of the first and second gate electrodes and the third and fifth semiconductor layers with high accuracy without alignment of mask pattern.
In the method of manufacturing a semiconductor device of the third aspect of the present invention, since the first and second gate electrodes are formed at the same time as part of the single gate electrode, a device in which the first and second gate electrodes are electrically connected to each other can be achieved through a simple process.
In the method of manufacturing a semiconductor device of the fourth aspect of the present invention, the third and fifth semiconductor layers and moreover the eighth semiconductor layer can be formed at the same time by implanting the impurity with the first and second gate electrodes as shields. That brings, as an effect, an efficient manufacture with less number of process steps, and makes it possible to determine the positional relation between the portion in the exposed surface of the second semiconductor layer covered with neither the first gate electrode nor the second gate electrode and the eighth semiconductor layer with high accuracy without alignment of mask pattern.
In the method of manufacturing a semiconductor device of the fifth aspect of the present invention, the seventh and eighth semiconductor layers are formed at the same time by implanting the impurity with a single shield. That makes it possible to efficiently manufacture the device comprising the eighth semiconductor layer with less number of process steps.